Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit involves numerous processing steps. A gate dielectric, typically formed from silicon dioxide, is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate electrode is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form source and drain regions. A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modern day semiconductor microelectronic fabrication processes form features having less than 0.25 critical dimensions, for example in future processes even less than 0.13 microns. As feature size decreases, the size of the resulting transistor as well as transistor features also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single die area.
In semiconductor microelectronic device fabrication, polysilicon and silicon dioxide (SiO2) are commonly used to respectively form gate electrodes and gate dielectrics for metal-oxide-semiconductor (MOS) transistors. As device dimensions have continued to scale down, the thickness of the SiO2 gate dielectric layer has also decreased to maintain the same capacitance between the gate and channel regions. A thickness of the gate oxide layer of less than 2 nanometers (nm) will be required to meet smaller device design contraints. A problem with using SiO2 as the gate dielectric is that thin SiO2 oxide films may break down when subjected to electric fields expected in some operating environments, particularly for gate oxides less than about 50 Angstroms thick. In addition, electrons more readily pass through an insulating gate dielectric as it gets thinner due to what is frequently referred to as the quantum mechanical tunneling effect. In this manner, a tunneling current, produces a leakage current passing through the gate dielectric between the semiconductor substrate and the gate electrode, increasingly adversely affecting the operability of the device. Another increasing problem is the formation of trapping states and interfacial charged states at the silicon/gate dielectric interface which increasingly adversely affects device electrical characteristics. For example, as the trapped charges accumulate over time, the threshold voltage VT may shift from its design specification. Dielectric breakdown of thinner gate dielectrics is also likely to occur at lower values of applied gate voltage in part due to an increase in the relative volume of defects in the gate dielectric. Such defects have an increasingly adverse effect as the gate dielectric gets thinner. For example, a thin gate oxide often includes defects due to uneven growth of the gate oxide due to defects at the silicon surface.
Because of high direct tunneling currents, SiO2 films thinner than 1.5 nm cannot be used as the gate dielectric in CMOS devices. There are currently intense efforts to replace SiO2 with high-k (high dielectric constant) dielectrics, including for example, TiO2, Ta2O5, ZrO2, Y2O3, La2O5, HfO2, and their aluminates and silicates attracting the greatest attention. A higher dielectric constant gate dielectric allows a thicker gate dielectric to be formed which dramatically reduces tunneling current and consequently gate leakage current, thereby overcoming a severe limitation in the use of SiO2 as the gate dielectric. While silicon dioxide (SiO2) has a dielectric constant of approximately 4, other candidate high-k dielectrics have significantly higher dielectric constant values of, for example, 20 or more. Using a high-k material for a gate dielectric allows a high capacitance to be achieved even with a relatively thick dielectric. Typical candidate high-k dielectric gate oxide materials have high dielectric constant in the range of about 20 to 40.
There have been, however, difficulties in forming high-k gate oxide dielectrics to achieve acceptable processing integration between the high-k gate dielectric and the polysilicon electrode formed overlying the high-k gate dielectric. For example, post deposition annealing treatments of high-k dielectric layers in the presence of oxygen have been found to detrimentally affect high-k dielectric films by leading to crystallization of the film and formation of an interfacial SiO2 layer during the annealing treatment. SiO2 interfacial layer formation at material layer interfaces creates a low dielectric constant layer in series with the high dielectric layer and therefore reduces the effective capacitance of the stacked layers.
Another problem associated with the above-mentioned high-k dielectrics is that the forming of a crystalline structure under normal preparation conditions leads to a roughened film surface. Surface roughness causes non-uniform electrical fields in the channel region adjacent the dielectric film. Such films are not suitable for the gate dielectrics of MOSFET devices.
Other processing difficulties with high-k dielectric materials include the tendency that high-k dielectric materials are relatively difficult to etch, unlike a conventional thermally grown oxide. Chemical etchants used with high-k materials may cause damage to associated oxide materials making high temperature rapid thermal oxidation (RTO) processes necessary to repair such damage while leading to the undesirable effect of crystallization of an amorphous high-k dielectric film. Proposed solutions to improve processing condition for forming high-k gate dielectrics with acceptable electrical properties, such as capacitance and leakage current, have included efforts to improve the thermal stability of the high-k dielectric films thereby avoiding film crystallization, or to provide processes whereby lower process temperatures (lower thermal budgets) are achieved, which have met with limited success.
Therefore it would be advantageous to develop a reliable method and structure for forming high-k gate dielectrics with associated gate electrodes that overcome the shortcomings of the prior art including improved electrical properties.
It is therefore an object of the invention to provide a reliable method for forming high-k gate dielectrics with associated gate electrodes that overcome the shortcomings of the prior art including improved electrical properties.